1. Field of the Invention
The invention relates to a digital sigma-delta modulator with multi-phase operations by time-shared means including an adder to produce multiple integration.
2. Background Information
Such a second-order modulator based on a double-loop configuration but with the digital integrators implemented by add and store structures using a time-shared arithmetic unit having two phases of operation corresponding to the two integrations is outlined in the IEEE Journal of Solid-State Circuits, Vol. 24, No 2, April 1989, p. 274 to 280, particularly on p. 278, as part of a dual-channel voice-band PCM codec. The basic configuration shown differs from the classical double-loop circuit in that the output integrator has its delay circuit not in the forward path, immediately after the adder, but in the feedback loop as for the input integrator, a third delay circuit being added between the output integrator and the quantizer. In other words, one keeps a delay circuit in the forward path, but since it is shifted beyond the feedback loop, the latter also includes a delay circuit to keep the equivalence with the classical circuit. The latter is for instance discussed in the IEEE Transactions on Communications, Vol.COM-33, No 3, March 1985, p. 249 to 258, where the advantages of double integration in conjunction with two-level quantization are explored in relation to more general structures having three or more feedback loops and quantizers not limited to two levels only. In the first article mentioned above, the digital delay circuits are used as registers with the content of the first added to the digital input signal during a first phase of operation. The result is used to update this first register and it is added to the content of the second register. The quantization is achieved by taking the sign bit from the second register. The 1-bit subtraction of the quantizer bit is done by bit manipulation of the Most Significant Bit of the input signal for the first phase and of the input coming from the first register during phase two. Bit manipulations, by combinational logic techniques on the MSBs of the two numbers of which the difference is to be obtained without performing a full subtraction operation, is for instance disclosed in the U.S. Pat. No. 4209773 as well as in the IEEE Transactions on Communications, Vol.COM-27, No 2, February 1979, p. 283 to 295, particularly on p. 288 describing a single loop digital Delta Sigma Modulator part of a single-channel PCM codec. This uses 2's complement arithmetic with parallel bit operations as is also the case in the U.S. Pat. No. 4270027 on a telephone subscriber line unit with sigma-delta digital to analog converter where only an adder, without an additional subtractor, is disclosed, e.g. in FIG. 5 of that patent, for the single loop digital integration.
The solution of the first article using a time-shared arithmetic unit for a second-order Digital Sigma-Delta Modulator starting from a double-loop circuit configuration, with the input and output integrators each including registers providing feedback loop delays, implies two separate registers each with associated input and output switches enabling appropriate connections to the adder and to the digital sigma-delta modulator (hereafter referred to as DSDM) input during the two phases of operations. Especially when implementing such a time-shared solution in a dedicated structure not relying on a time-shared arithmetic unit used also for other purposes, it would be desirable to avoid three 2-way switches to interconnect the adder inputs and output with the two registers and with the DSDM input in the way appropriate to the two phases of operations. This is all the more true with a bit-slice architecture, e.g. with operations on 17 bits in parallel, if one wishes to minimize the area of the chip, e.g. CMOS. Likewise, savings with respect to the two separate registers solution would help to achieve that goal.
Instead of the modified architecture of the basic second-order double-loop DSDM, used in the first article for a time-shared approach, it is also known to have the delay circuit of the input integrator not in the feedback loop but in the forward path, immediately after the adder, as for the output integrator. This is disclosed for instance in the IEEE Transactions on Communications, Vol. COM-31, No 3, March 1983, p.360 to 369, as well as in the IEEE Journal of Solid-State Circuits, Vol. 23, No 6, December 1988, p. 1298 to 1308, particularly p.1300 discussing the extraction of this modified structure from the conventional one.